The total energy consumption and carbon footprint of data centers will substantially increase in the next years after more than a decade of relative slow growths. This trend has been indicated by a new study modelling the carbon footprint of ICT in Germany within the framework of the GreenICT@FMD framework project. The keynote has two objectives. The first objective of the keynote is to provide an insight into the methodological approach to the lifecycle environmental assessment of computer systems. In this context, the factors that lead to increasing environmental impacts in the production and use of enterprise computers are explained in detail. This includes, among other things, topics such as the environmental impact of semiconductor production in the context of Moore's Law and the topic of the use of renewable energies. The second objective of the keynote addresses the immediate factors that are currently contributing to a rapid increase in computer power consumption in data centers. Using the example of the current technical development of high-end CPUs, the declining of server-related energy efficiency is analyzed. Other topics include trends concerning chip cooling and waste heat utilization in data centers. The keynote intends to provide a holistic perspective on the environmental aspects of higher performing computer systems.

Lutz Stobbe is a senior scientist at the Fraunhofer Institute for Reliability and Microintegration (IZM) with 25 years of work experience in Green information and communication technology (ICT). The research of his group, “Sustainable Networks and Computing'', is focused on the methodical issues of lifecycle assessment (LCA) and applied eco-design for data center and telecommunication equipment. He developed the 5C methodology, which supports a structured modelling of complex lifecycle inventories. As a project manager, he has been involved in dozens of national and international research projects. Most notably are six preparatory studies developing measures for the implementation of the EU Ecodesign Directive. This includes the ENTR Lot 9 study on enterprise servers and data storage equipment. He also led expert teams (Begleitforschung) accompanying large publicly funded research programs such as IT2Green, 5G Industrial Internet, Green HPC, and Green ICT. His work for industry includes trainings and consultations, focusing on applied LCA and eco-design.

Parallel computing is ubiquitous and can be found in a wide variety of applications, from high-performance computing to embedded systems. A key factor across all these areas is energy efficiency, which denotes the number of computations that can be performed per unit of energy. Hence, customization and a tight co-design of architecture and compiler are crucial for scaling future systems further.

This talk presents tightly coupled processor arrays (TCPAs), a class of massively parallel arrays of locally interconnected processing elements (PEs), as well as corresponding compilation concepts. TCPAs differ from coarse-grained reconfigurable arrays (CGRAs) in that the PEs are programmable, utilizing small instruction memories. They allow for the parallel execution of multiple rather than just the innermost loop dimension of many computationally intensive applications. Besides introducing the main architectural building blocks of these arrays, the presentation covers the corresponding application mapping, which starts from a functional programming language and involves symbolic loop compilation. In this approach, the loop bounds and number of available PEs can be unknown at compile time. Finally, the talk reports on the research endeavor of prototyping an 8x8 TCPA instance as a chip manufactured in 22 nm technology.

Frank Hannig received a Diploma degree in an interdisciplinary course of study in electrical engineering and computer science from the University of Paderborn, Germany, in 2000; a Ph.D. degree (Dr.-Ing.) and a Habilitation degree in computer science from Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany, in 2009 and 2018, respectively. He has led the Architecture and Compiler Design Group in the Computer Science Department at FAU since 2004. His primary research interests are the design of massively parallel architectures, ranging from dedicated hardware to multicore architectures, mapping methodologies for domain-specific computing, and architecture/compiler co-design. He has authored or co-authored more than 200 peer-reviewed publications. Dr. Hannig has served on the program committees of several international conferences (ARC, ASAP, CODES+ISSS, DAC, DATE, DASIP, SAC, SAMOS) and is an associate editor of the Journal of Real-Time Image Processing and IEEE Embedded Systems Letters. He is a Senior Member of the IEEE and an affiliate member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).