17th Workshop on Dependability and Fault Tolerance (VERFE 2023)
organized as Special Track in conjunction with 36th ARCS 2023
Athens, Greece, June 13-15, 2023

Background and Focus

Although the basic reliability of hardware and software components has improved over decades, their increasing number causes severe problems. Moreover, in recent years it can be observed that an increasing number of devices are integrated into environments of other physical components such as automotive or digital systems. Here, the complexity and number of interactions with these components creates problems with regard to maintaining a dependable operation of the entire system in case of faults or external disturbances. While this is not a problem with microprocessors, shrinking feature sizes, higher complexity, lower voltages, and higher clock frequencies increase the probability of design, manufacturing and operational faults, making fault tolerance techniques in general purpose processors to be of crucial importance in the future. As simple solutions (such as TMR) can easily get too expensive, the ability to trade increased reliability against performance/power overhead will become important, resulting in light-weight fault tolerance techniques implemented in hardware, but controllable from higher software layers.

This workshop aims at presenting contributions and work-in-progress from the research area of dependable and fault-tolerant computing in order to bring together scientists working in related fields.

Topics

Contributions on the topic of “Dependable Embedded Systems“ are of particular interest; contributions
on general topics of dependability and fault tolerance are also welcome but not limited to:

• dependable computer systems, networks and embedded systems
• dependability of mechatronic systems
• fault-tolerant systems and system components
• safety-critical applications
• highly available systems
• real-time and performance guarantees
• testing of hardware and software
• fault detection and fault treatment
• failure prediction
• modeling, simulation and evaluation of fault-tolerant systems
• reliability models for hardware and software
• validation and verification
• fault models and fault abstraction
• fault injection techniques
• on-chip fault-tolerance
• software-controlled fault tolerance
• fault-tolerant processor architecture
• fault-tolerance in operating systems, storage and database systems

Two kinds of contributions are welcome:

• research papers documenting results of scientific investigations and
• position papers proposing strategies or discussing open problems.

Informations for Authors

Authors are invited to submit original, unpublished papers via Easychair. The main conference ARCS 2023 uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliation. When citing own work, it must be done in a neutral form (i.e. avoiding ‘our’, ‘we’, ‘previous work’ etc.). Papers must be submitted in PDF format, formatted according to Springer LNCS style and must not exceed 15 pages, including references, appendices and figures. Accepted contributions will be part of the conference proceedings. The proceedings of ARCS 2023 are published in the Springer Lecture Notes on Computer Science (LNCS) series. Selected papers will be invited for a Special Issue in the Elsevier Journal of System Architecture.

Deadlines

Workshop / Track Chairs

Technical Program Committee