Background and Focus Although the basic reliability of hardware and software components has improved over decades, their increasing number causes severe problems. Moreover, in recent years it can be observed that an increasing number of devices are integrated into environments of other physical components such as cars or digital systems. Here, the complexity and number of interactions with these components creates problems with regard to maintaining a dependable operation of the entire system in case of faults or external disturbances. While this is not a problem with microprocessors, shrinking feature sizes, higher complexity, lower voltages, and higher clock frequencies increase the probability of design-, manufacturing-, and oper-
ational faults, making fault tolerance techniques in general purpose processors to be of crucial importance in the future. As simple solutions (such as TMR) can easily get too expensive, the ability to trade increased reliability against performance/power overhead will become important, resulting in light-weight fault tolerance techniques implemented in hardware, but controllable from higher software layers. This workshop aims at presenting contributions and work-in-progress from the research area of dependable and fault-tolerant computing in order to bring together scientists working in related fields.
Topics Contributions on the topic of “Dependable Embedded Systems“ are of particular interest; contributions on general topics of dependability and fault tolerance are also welcome but not limited to:
- reliability models for hardware and software
- modeling and simulation of fault-tolerant systems
- fault-tolerant systems and system components
- testing of hardware and software
- failure prediction and fault treatment
- detection and correction of transient faults
- quantitative assessment of reliability improvements
- safety-critical applications
- timeliness problems
- dependability of networks
- dependability of embedded systems
- dependable organic computing
- highly available systems
- self-organization within redundant systems
- dependable ubiquitous and pervasive computing
- composability of dependable systems
- dependable mechatronic systems / micro systems
- dependability of mobile and wireless systems
- robustness and robustness metrics
- validation and verification
- fault models and fault abstraction
- fault injection techniques
- software-controlled fault tolerance
- on-chip backward recovery techniques
- forward recovery techniques
- fault-tolerant caching mechanisms
- dynamic re-use of currently unused resources in processors for fault-tolerance
The workshop will focus on research presentations as well as brainstorming sessions.
Therefore, two kinds of contributions are welcome:
- research papers documenting results of scientific investigations and
- position papers proposing strategies or discussing open problems.
Informations for Authors
Accepted papers will be published by VDE and IEEExplore.
Papers should be in English and formatted according to IEEE eXpress ”conference mode”.
Selected papers will appear in the FERS Journal (ISSN 0724-5319).
Submission: April 30th , 2021 (ext. abstracts (3-4 pages) or full papers (max. 8 pages), PDF) to: firstname.lastname@example.org
Notification: May 10 th , 2021
Camera-ready: May 24 th , 2021 (max. 8 pages)
The aerospace market has undergone rapid changes within the last 15 years. Due to technological progress in consumer electronics satellite design has evolved from the purely use of customized hardware solutions towards the utilization of commercial off-the-shelf electronics, potentially leading to higher cost efficiency and an increased system performance. The dawn of the CubeSats and upcoming Mega-Constellations of miniaturized satellites are currently fueling the progress, attracting venture capital in a never seen before ratio. Mega-Constellations of satellites for a diverse range of applications have become reality with the successful funding of OneWeb and other small satellite swarms. While using COTS electronics, such missions require an increased level of dependability in all subsystems to enable their use within critical missions and for such with prolonged lifetime requirements. However, miniaturized satellites are plagued by low dependability, and require failure tolerance and reliability-enhancing measures to be implemented. Furthermore, on board computers of such spacecraft need to take into account specific boundary conditions which can differ significantly from those of standard computing systems. These comprise environmental factors like launch loads or radiations robustness but also limitations regarding power consumption, mass or costs. The workshop will discuss existing and novel approaches for computer architectures in space, targeting an audience from computer architects to space engineers working on miniaturized as well as traditional larger scale satellites. Synergies to existing terrestrial applications as well as computing architectures of constellations and swarms of satellites are a focus of the workshop, being firmly embedded in the main conference. The ARCS conferences series has over 30 years of tradition reporting leading edge research in computer architecture and operating systems.
Topics of Interest
Contributions on the topic of “Architecture of spaceflight on board computers“ are of particular interest but not limited to:
- Dependable spacecraft and payload computer architectures
- Mitigation of radiation induced errors
- Space Mission results and lessons learned
- Modified COTS solutions
- Fault detection and fault mitigation
- Fault tolerance techniques and strategies in space environments
- Computer architectures in spaceflight
- Computing on Nano- and Femtosatellites
- Constellations and Swarms
- Real Time and fault tolerance on COTS solutions
- Parallel and Distributed Computing in space
- Cloud Computing and Big Data in space applications
- Validation, Certification, Testing and test results
Accepted papers will be published by VDE Verlag and IEEExplore Digital Libray. The workshop will focus on research presentations as well as brainstorming sessions. Therefore, two kinds of contributions are welcome:
- research papers documenting results of scientific investigations, and
- position papers proposing strategies or discussing open problems.
Submission: Deadline: April 15, 2021 full papers 6-8 Pages, IEEE Format, PDF) Submission via EasyChair
Notification: May 10th, 2021
Camera-ready:May 24th, 2021 (max. 8 pages, LaTeX Source or Word);
Papers will appear in ARCS 2021 Workshop Proceedings.
- Papers should be in English and formatted according to IEEE eXpress "conference mode".
- Please refer to IEEE: www.ieee.org/conferences_events/conferences/publishing/templates.html.
- Papers should not exceed 8 pages (full paper) behaviour
Please refer to the ARCS 2021 web site for registration and venue information.
Automotive and avionic industry demands more and more processor performance to satisfy the requests of their consumers. Semiconductor manufactures are forced to move to multi and many-core embedded processors to provide this compute power. However, embedded legacy software and certificate constraints hinder the distribution of safe, reliable, and secure software for many/multi-core systems. On the other side, this development cannot be reversed anymore.
The FORMUS3IC research community is in its core a consortium from academia and industry funded from Bavarian Research Foundation that pursues to find answers for the challenges arising by using multi-/many-core processors in future automotive and avionics tasks. The community intends to expand its orientation more and more to the international community and invites researchers working on challenges for automotive and avionic applications using heterogeneous architectures to join. To face these challenges a holistic approach is addressed containing software requirements specification, e.g. given in adaptive AUTOSAR or EAST-ADL, safety and security aspects for embedded heterogeneous architectures, sensor fusion applications, performance modelling and parallel design patterns using embedded CPUs, special cores, embedded GPUs and FPGAs to provide both performance and low energy consumption. Papers addressing the following and other related topics to multi-/many-core challenges for automotive and avionics are welcome:
- Software and Hardware Architectures for ADAS
- Functional Safety, IT-Security and Verification
- Parallel Embedded Programming
- Architecture Modelling and Time Simulation
- Performance Engineering Methods for Embedded Automotive and Avionics Software
- Virtual Design Platforms for Automotive and Avionics
- Parallel Design Patterns and Parallelization Techniques
- New Techniques for Safety, Security and Task Scheduling
- WCET analysis and tools for WCET estimation
- NoCs and Communication Architectures for Safety-critical Systems
- Parallel Embedded Programming
- Real-Time Operating Systems for Automotive and Avionics
- Data Processing based Fusion of Multi-sensory Information like Radar, Ultra-sonic and Visual Information
- Determination of non-functional Properties like Energy Consumption and Response Time during Design Time
- Heterogeneous GPU / Multi-core Microcontroller Architectures for Embedded Vision and Signal Processing
Information for Authors
Accepted papers will be printed as Springer publication, same as ARCS Springer publication!
They should be formatted according to Springer LNCS style (see:https://www.springer.com/gp/computer-
science/lncs/conference-proceedings-guidelines) and must not exceed 12 pages, including references and figures.
Please submit your full papers to EasyChair
Submission deadline:15 th April 2021
Notification: 10 th May 2021
Camera-ready version:24 th May 2021
Dietmar Fey, FAU Erlangen, DE
Jürgen Mottok, LaS3, ZD.B, OTH Regensburg, DE